`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/26 22:32:06
// Design Name: 
// Module Name: E_M
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module E_M(
    input logic              clk,res,
    input logic              clr,
 
    input logic [31: 0]      pc_e,
    input logic              memtoreg_e,
    input logic              memwrite_e,
    input logic              regwrite_e,
    input logic [31: 0]      alu_res_e,
    input logic [31: 0]      write_data_e,
    input logic [ 4: 0]      write_reg_e,
    input logic [ 1: 0]      hilowrite_e,
    input logic [63: 0]      hilo_o_e, 
    input logic [31: 0]      cp0_data_e,
    input logic              cp0_we_e,
    input logic [ 7: 0]      cp0_wadr_e,
    input logic [ 3: 0]      store_sel_e,
    input logic [ 3: 0]      load_type_e,
    input logic              res_src_e,
    input logic [`EXCS_BUS]  excs_e,
    input logic              inslot_e,

    output logic [31: 0]     pc_m,
    output logic             memtoreg_m,
    output logic             memwrite_m,
    output logic             regwrite_m,
    output logic [31: 0]     alu_res_m,
    output logic [31: 0]     write_data_m,
    output logic [ 4: 0]     write_reg_m,
    output logic [ 1: 0]     hilowrite_m,
    output logic [63: 0]     hilo_o_m,
    output logic [31: 0]     cp0_data_m,
    output logic             cp0_we_m,
    output logic [ 7: 0]     cp0_wadr_m,
    output logic [ 3: 0]     store_sel_m,
    output logic [ 3: 0]     load_type_m,
    output logic             res_src_m,
    output logic [`EXCS_BUS] excs_m,
    output logic             inslot_m
    );

    always @(posedge clk,posedge res) begin
        if (res) begin
            pc_m            <= 32'b0;
            memtoreg_m      <= 1'b0;
            memwrite_m      <= 1'b0;
            regwrite_m      <= 1'b0;
            alu_res_m       <= 32'b0;
            write_data_m    <= 32'b0;
            write_reg_m     <= 5'b0;
            hilowrite_m     <= 2'b0;
            hilo_o_m        <= 63'b0;
            cp0_data_m      <= 32'b0;
            cp0_we_m        <= 1'b0;
            cp0_wadr_m      <= 8'b0;
            store_sel_m     <= 4'b0;
            load_type_m     <= 4'b0;
            res_src_m       <= 1'b0;
            excs_m          <= 0;
            inslot_m        <= 1'b0;
        end
        else if (clr) begin
            pc_m            <= 32'b0;
            memtoreg_m      <= 1'b0;
            memwrite_m      <= 1'b0;
            regwrite_m      <= 1'b0;
            alu_res_m       <= 32'b0;
            write_data_m    <= 32'b0;
            write_reg_m     <= 5'b0;
            hilowrite_m     <= 2'b0;
            hilo_o_m        <= 63'b0;
            cp0_data_m      <= 32'b0;
            cp0_we_m        <= 1'b0;
            cp0_wadr_m      <= 8'b0;
            store_sel_m     <= 4'b0;
            load_type_m     <= 4'b0;
            res_src_m       <= 1'b0;
            excs_m          <= 0;
            inslot_m        <= 1'b0;
        end 
        else begin
            pc_m            <= pc_e;
            memtoreg_m      <= memtoreg_e;
            memwrite_m      <= memwrite_e;
            regwrite_m      <= regwrite_e;
            alu_res_m       <= alu_res_e;
            write_data_m    <= write_data_e;
            write_reg_m     <= write_reg_e;
            hilowrite_m     <= hilowrite_e;
            hilo_o_m        <= hilo_o_e;
            cp0_data_m      <= cp0_data_e;
            cp0_we_m        <= cp0_we_e;
            cp0_wadr_m      <= cp0_wadr_e;
            store_sel_m     <= store_sel_e;
            load_type_m     <= load_type_e;
            res_src_m       <= res_src_e;
            excs_m          <= excs_e;
            inslot_m        <= inslot_e;
        end
    end
endmodule
